Field of the Invention
This invention relates generally to the field of computer processors. More particularly, the invention relates to an apparatus and method for parallel pixel shading.
Description of the Related Art
The pixel shader stage in a graphics pipeline may operate on pixel quads or pixel groups (e.g., 2×2 groups, 4×4 groups, etc). Dividing the screen space equally among concurrent hardware allows for concurrent execution of mutually exclusive pixels. The screen space can be statically mapped to the group of computing units (sometimes referred to as execution units (“EUs”)) to achieve this mutual exclusion and parallelism. Three-way hashing enables efficient selection of computing resources to achieve a desired power/performance target for a graphics instruction pipeline.